Benjamin Barzen 8611429237 ABC9: Cell Port Bug Patch (#3670) ...

* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>

2023-04-22 16:24:36 -07:00

..

anlogic

anlogic: support BRAM mapping

2021-12-17 20:28:22 +08:00

common

Removing extra default_nettype lines

2023-02-21 05:23:16 +13:00

ecp5

Genericising bug1836.ys

2023-02-21 05:23:16 +13:00

efinix

efinix: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

fabulous

fabulous: Add support for mapping carry chains

2023-02-27 09:50:34 +01:00

gatemate

Testing TDP synth mapping

2023-02-21 05:23:15 +13:00

gowin

gowin: Fix LUT RAM inference, add more models.

2022-02-09 09:04:34 +01:00

ice40

Tests for ram_style = "huge"

2023-02-21 05:23:15 +13:00

intel_alm

Fix for sync_ram_sdp not being final module

2023-02-21 05:23:16 +13:00

machxo2

add additional dff and lutram tests

2023-04-06 09:10:14 +02:00

nexus

nexus: Use memory_libmap pass.

2022-05-18 17:32:56 +02:00

quicklogic

quicklogic: ABC9 synthesis

2021-04-17 20:54:58 +02:00

xilinx

ABC9: Cell Port Bug Patch (#3670)

2023-04-22 16:24:36 -07:00

run-test.sh

Add default assignments to SB_LUT4

2021-04-20 12:46:21 +02:00