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04d2f55bec69d551d344d7ba5d3ec25535b8a97e
YosysHQ.yosys
/
techlibs
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quicklogic
/
pp3
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N. Engelhardt
e230a871be
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
..
abc9_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
abc9_model.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
abc9_unmap.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
cells_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
ffs_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
latches_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
lut_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
