github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-25 03:46:21 +00:00
Code Issues Releases Wiki Activity
Files
04de9bb6551307421ce21ba87a98d50c2d10b07a
YosysHQ.yosys/backends/verilog
History
Marcelina Kościelnicka 56e7791760 verilog backend: Emit a wire for ports as well. 
Fixes #3177.
2022-01-31 01:08:41 +01:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
verilog backend: Emit a wire for ports as well.
2022-01-31 01:08:41 +01:00