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YosysHQ.yosys/tests/arch/common/add_sub.v
Miodrag Milanovic 9bd9db56c8 Unify verilog style
2019-10-18 12:50:24 +02:00

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151 B
Verilog

module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule