YosysHQ.yosys/tests/memlib/memlib_block_sdp.txt

ram block \RAM_BLOCK_SDP {
	cost 64;
	abits 10;
	widths 1 2 4 8 16 per_port;
	init any;
	port sw "W" {
		clock anyedge;
	}
	port sr "R" {
		clock anyedge;
	}
}