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YosysHQ.yosys/tests/simple/lesser_size_cast.sv
2022-01-03 08:17:35 -07:00

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Systemverilog

module top (
input signed [1:0] a,
input signed [2:0] b,
output signed [4:0] c
);
assign c = 2'(a) * b;
endmodule