Krystine Sherwin 064723a1cc example_synth: tidying ...

Adds note on `+/`.
Clarifies that we can't entirely skip loading `cells_sim.v`, and then mentions it again later once we need it.
More on final steps (and synthesis outputs).

2024-01-13 15:46:00 +13:00

..

source

example_synth: tidying

2024-01-13 15:46:00 +13:00

util

Some tidy up

2023-08-14 12:13:29 +12:00

.gitignore

docs: restructuring images directory

2023-11-14 18:54:16 +13:00

Makefile

Rst docs conversion (#3496)

2022-11-15 12:55:22 +01:00