github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-01 14:42:19 +00:00
Code Issues Releases Wiki Activity
Files
0795b3ec076d8d2c0aa0d954b707271bd2f064bf
YosysHQ.yosys/tests
History
Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling 
- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
intel_alm: Fix illegal carry chains
2021-05-15 22:37:06 +01:00
asicworld
Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-25 16:18:13 -08:00
blif
tests/blif: Add missing gitignore
2021-05-20 12:49:51 +02:00
bram
tests/bram: Do not generate write address collisions.
2021-03-08 16:53:03 +01:00
errors
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
…
liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memories
tests: Parallelize
2020-09-21 15:07:02 +02:00
opt
opt_mem_feedback: Respect write port priority.
2021-05-25 15:59:41 +02:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
realmath
…
rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
assertpmux: Fix crash on unused $pmux output.
2021-02-22 23:30:28 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
…
simple
verilog: fix case expression sign and width handling
2021-05-25 16:16:46 -04:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
…
sva
Fix "verific -extnets" for more complex situations
2019-03-26 14:17:46 +01:00
svinterfaces
Fix typo in tests/svinterfaces/runone.sh
2019-05-03 14:40:51 +02:00
svtypes
verilog: check entire user type stack for type definition
2021-03-21 19:35:13 -04:00
techmap
Add tests for some common techmap files.
2021-02-24 01:07:34 +01:00
tools
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
unit
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
various
abc9: uniquify blackboxes like whiteboxes (#2695)
2021-03-29 22:02:06 -07:00
verilog
sv: check validity of package end label
2021-05-10 14:37:32 -04:00
vloghtb
…
gen-tests-makefile.sh
tests: Parallelize
2020-09-21 15:07:02 +02:00