github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-02-25 16:41:06 +00:00
Code Issues Releases Wiki Activity
Files
081d9318bcf1ee13549ddcb0983cba5f00b4272c
YosysHQ.yosys/techlibs/ice40
History
whitequark 3f4460a186 ice40: match memory inference attribute values case insensitive. 
LSE/Synplify use case insensitive matching.
2020-02-06 14:58:20 +00:00
..
tests
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
2019-08-12 12:06:45 -07:00
.gitignore
Initialization support for all iCE40 bram modes
2015-04-26 08:39:31 +02:00
abc9_hx.box
Cleanup ice40 boxes
2019-12-31 18:29:37 -08:00
abc9_hx.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_lp.box
Cleanup ice40 boxes
2019-12-31 18:29:37 -08:00
abc9_lp.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_model.v
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
abc9_u.box
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
abc9_u.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
2020-01-24 11:59:48 -08:00
brams_init.py
Switched to Python 3
2015-08-22 09:59:33 +02:00
brams_map.v
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 16:23:40 -08:00
brams.txt
ice40: match memory inference attribute values case insensitive.
2020-02-06 14:58:20 +00:00
cells_map.v
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
2020-01-27 13:30:27 -08:00
cells_sim.v
ice40: add SB_SPRAM256KA arrival time
2020-01-24 12:17:09 -08:00
dsp_map.v
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
2019-08-08 12:56:05 -07:00
ice40_braminit.cc
substr() -> compare()
2019-08-07 12:20:08 -07:00
ice40_ffinit.cc
ice40: Demote conflicting FF init values to a warning
2019-12-31 02:38:10 +01:00
ice40_ffssr.cc
ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-08 22:46:28 +01:00
ice40_opt.cc
Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
2020-01-27 14:02:13 -08:00
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Makefile.inc
Makefile: don't assume python is called python3
2019-10-19 14:04:52 +08:00
synth_ice40.cc
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00