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YosysHQ.yosys/tests/various/design_equal_fail.ys
2025-12-21 21:47:40 +00:00

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logger -expect error "Second design missing module top_renamed" 1
read_rtlil <<EOT
module \top
wire width 1 input 1 \a
wire width 1 output 2 \y
connect \y \a
end
EOT
design -save golden
design -reset
read_rtlil <<EOT
module \top_renamed
wire width 1 input 1 \a
wire width 1 output 2 \y
connect \y \a
end
EOT
design_equal golden