Sylvain Munaut 4f9183d107 ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

2019-05-13 12:51:06 +02:00

..

tests

Bugfix in ice40_dsp

2019-02-21 13:28:46 +01:00

.gitignore

Initialization support for all iCE40 bram modes

2015-04-26 08:39:31 +02:00

arith_map.v

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

brams_init.py

Switched to Python 3

2015-08-22 09:59:33 +02:00

brams_map.v

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

2019-02-28 16:23:40 -08:00

brams.txt

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

cells_map.v

Improving vpr output support.

2018-04-18 16:55:12 -07:00

cells_sim.v

ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC

2019-05-13 12:51:06 +02:00

ice40_braminit.cc

Fix typo in ice40_braminit help msg

2019-03-09 13:24:55 -08:00

ice40_ffinit.cc

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

ice40_ffssr.cc

ice40: Honor the "dont_touch" attribute in FFSSR pass

2018-12-08 22:46:28 +01:00

ice40_opt.cc

Extract ice40_unlut pass from ice40_opt.

2018-12-05 16:30:24 +00:00

ice40_unlut.cc

Extract ice40_unlut pass from ice40_opt.

2018-12-05 16:30:24 +00:00

latches_map.v

Added synth_ice40 support for latches via logic loops

2016-05-06 23:02:37 +02:00

Makefile.inc

ice40: Add ice40_braminit pass to allow initialization of BRAM from file

2019-03-08 00:15:46 +01:00

synth_ice40.cc

Merge pull request #969 from YosysHQ/clifford/pmgenstuff

2019-05-03 20:39:50 +02:00