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0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47
YosysHQ.yosys/tests
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Claire Xenia Wolf 0ada13cbe2 Use HTTPS for website links, gatecat email 
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
2021-06-09 12:16:56 +02:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
asicworld
Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-25 16:18:13 -08:00
blif
tests/blif: Add missing gitignore
2021-05-20 12:49:51 +02:00
bram
tests/bram: Do not generate write address collisions.
2021-03-08 16:53:03 +01:00
errors
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memories
tests: Parallelize
2020-09-21 15:07:02 +02:00
opt
memory_map: Improve start_offset handling.
2021-05-31 17:45:21 +02:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
realmath
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
assertpmux: Fix crash on unused $pmux output.
2021-02-22 23:30:28 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
simple
verilog: fix case expression sign and width handling
2021-05-25 16:16:46 -04:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
Progress in SMV back-end
2015-06-19 14:08:46 +02:00
sva
Fix "verific -extnets" for more complex situations
2019-03-26 14:17:46 +01:00
svinterfaces
Fix typo in tests/svinterfaces/runone.sh
2019-05-03 14:40:51 +02:00
svtypes
verilog: check entire user type stack for type definition
2021-03-21 19:35:13 -04:00
techmap
Add tests for some common techmap files.
2021-02-24 01:07:34 +01:00
tools
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
unit
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
various
abc9: uniquify blackboxes like whiteboxes (#2695)
2021-03-29 22:02:06 -07:00
verilog
sv: support tasks and functions within packages
2021-06-01 13:17:41 -04:00
vloghtb
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
gen-tests-makefile.sh
tests: Parallelize
2020-09-21 15:07:02 +02:00