Clifford Wolf 2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays

2019-06-20 12:03:00 +02:00

..

.gitignore

Add "make coverage"

2018-08-27 14:22:21 +02:00

const2ast.cc

Added support for unsized constants, fixes #1022

2019-05-27 11:42:10 +02:00

Makefile.inc

Read bigger Verilog files.

2019-05-18 14:20:30 +03:00

preproc.cc

Support SystemVerilog `` extension for macros

2018-05-17 00:09:56 -04:00

verilog_frontend.cc

Add "read_verilog -pwires" feature, closes #1106

2019-06-19 14:38:50 +02:00

verilog_frontend.h

Add specify parser

2019-04-23 21:36:59 +02:00

verilog_lexer.l

Fixed brojen $error()/$info/$warning() on non-generate blocks

2019-06-11 02:52:06 +03:00

verilog_parser.y

Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays

2019-06-20 12:03:00 +02:00