This website requires JavaScript.
Explore
Help
Register
Sign In
github.com
/
YosysHQ.yosys
Watch
1
Star
0
Fork
0
You've already forked YosysHQ.yosys
mirror of
synced
2026-05-24 06:01:09 +00:00
Code
Issues
Releases
Wiki
Activity
Files
0eb215dd97377ab91bd00ca3e6d6786e82fd5c2d
YosysHQ.yosys
/
techlibs
/
intel
History
nella
fff034d2f8
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
…
cycloneiv
…
cycloneive
…
max10
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
Makefile.inc
…
synth_intel.cc
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00