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YosysHQ.yosys/frontends/verilog
Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals.
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
..
2018-08-27 14:22:21 +02:00
2025-05-08 10:37:04 +12:00