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YosysHQ.yosys/techlibs/xilinx
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Marcin Kościelnicki b44d0e041f xilinx: use RAM32M/RAM64M for memories with two read ports 
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
2020-02-02 14:34:21 +01:00
..
tests
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
.gitignore
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
abc9_map.v
Adding (* techmap_autopurge *) to FD* in abc9_map.v
2020-01-14 12:22:21 -08:00
abc9_model.v
Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
2020-01-22 14:22:03 -08:00
abc9_unmap.v
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 15:02:44 -08:00
abc9_xc7_nowide.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_xc7.box
Fix abc9_xc7.box comments
2020-01-07 17:00:38 -08:00
abc9_xc7.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623
2020-01-17 12:02:46 -08:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
cells_sim.v
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
cells_xtra.py
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
cells_xtra.v
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
lut_map.v
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
2020-01-27 13:30:27 -08:00
lutrams_map.v
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
2019-12-16 12:06:47 -08:00
lutrams.txt
xilinx: use RAM32M/RAM64M for memories with two read ports
2020-02-02 14:34:21 +01:00
Makefile.inc
xilinx: Add xilinx_dffopt pass (#1557)
2019-12-18 13:43:43 +01:00
mux_map.v
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
synth_xilinx.cc
synth_xilinx: cleanup help
2020-01-28 17:48:43 -08:00
xc3s_mult_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc3sda_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc6s_brams_map.v
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
xc6s_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc6s_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc6s_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_brams_map.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc7_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_xcu_brams.txt
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
xcu_brams_map.v
xilinx: Add support for UltraScale[+] BRAM mapping
2019-10-23 11:47:37 +01:00
xcu_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xcup_urams_map.v
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xcup_urams.txt
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xilinx_dffopt.cc
xilinx_dffopt: Keep order of LUT inputs.
2019-12-19 18:01:43 +01:00