gatecat 2b8f1633ce ecp5: Add DCSC blackbox ...

Signed-off-by: gatecat <gatecat@ds0.me>

2021-07-06 14:07:20 +01:00

..

tests

ecp5: Add simulation equivalence check for Diamond FF implementations

2019-08-30 13:27:36 +01:00

.gitignore

ecp5: Add support for mapping 36-bit wide PDP BRAMs

2019-10-01 13:46:36 +01:00

arith_map.v

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00

brams_connect.py

ecp5: Add support for mapping 36-bit wide PDP BRAMs

2019-10-01 13:46:36 +01:00

brams_init.py

ecp5: First BRAM type maps successfully

2018-10-10 16:35:19 +01:00

brams_map.v

remove unused parameters

2020-03-06 16:45:36 +01:00

brams.txt

ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.

2020-02-06 16:52:51 +00:00

cells_bb.v

ecp5: Add DCSC blackbox

2021-07-06 14:07:20 +01:00

cells_ff.vh

Fix bitwidth mismatch; suppresses iverilog warning

2019-12-11 13:02:07 -08:00

cells_io.vh

ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.

2019-08-30 10:05:09 +00:00

cells_map.v

ecp5: Use dfflegalize.

2020-07-05 18:49:41 +02:00

cells_sim.v

ecp5: TRELLIS_FF bypass path only in async mode

2020-05-14 10:33:56 -07:00

dsp_map.v

ecp5: Force SIGNED ports to be 1 bit

2020-04-16 16:38:19 +01:00

ecp5_gsr.cc

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00

latches_map.v

ecp5: Add latch inference

2018-10-19 15:16:40 +01:00

lutrams_map.v

synth_ecp5: rename dram to lutram everywhere.

2019-07-16 20:45:12 +00:00

lutrams.txt

ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.

2020-02-06 16:52:51 +00:00

Makefile.inc

ecp5: Use dfflegalize.

2020-07-05 18:49:41 +02:00

synth_ecp5.cc

Use HTTPS for website links, gatecat email

2021-06-09 12:16:56 +02:00