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YosysHQ.yosys/techlibs/xilinx
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Eddie Hung 33960dd3d8 Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
2019-08-20 12:55:26 -07:00
..
tests
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.gitignore
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abc_xc7_nowide.lut
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abc_xc7.box
Fix $__XILINX_MUXF78 box timing
2019-07-01 14:04:06 -07:00
abc_xc7.lut
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arith_map.v
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brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
xilinx: Fix missing cell name underscore in cells_map.v
2019-07-25 08:19:07 +01:00
cells_sim.v
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
cells_xtra.sh
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cells_xtra.v
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ff_map.v
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
2019-07-11 21:13:12 +02:00
lut_map.v
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lutrams_map.v
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
lutrams.txt
Work in progress for renaming labels/options in synth_xilinx
2019-07-18 14:20:43 -07:00
Makefile.inc
Update Makefile too
2019-07-18 14:51:55 -07:00
mux_map.v
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synth_xilinx.cc
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
2019-08-20 11:57:52 -07:00
xc6s_brams_bb.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc6s_brams_map.v
RST -> RSTBRST for RAMB8BWER
2019-07-29 16:05:44 -07:00
xc6s_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams_bb.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams_map.v
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
xc7_brams.txt
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00