12 lines
496 B
Verilog
12 lines
496 B
Verilog
(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
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module $__DFF_x__$abc9_flop (input C, D, Q, output n1);
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parameter _TECHMAP_CELLTYPE_ = "";
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generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
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$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
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else if (_TECHMAP_CELLTYPE_ == "$__DFF_P__$abc9_flop")
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$_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
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else if (_TECHMAP_CELLTYPE_ != "")
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$error("Unrecognised _TECHMAP_CELLTYPE_");
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endgenerate
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endmodule
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