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Catherine
1159e48721
write_verilog: emit
initial $display
correctly.
2024-01-11 13:13:04 +01:00
..
appendix
Remove docs dependency on yosys repo (
#3558
)
2022-11-24 15:56:44 +01:00
APPNOTE_011_Design_Investigation
Remove docs dependency on yosys repo (
#3558
)
2022-11-24 15:56:44 +01:00
CHAPTER_Prog
Remove docs dependency on yosys repo (
#3558
)
2022-11-24 15:56:44 +01:00
bib.rst
…
CHAPTER_Approach.rst
…
CHAPTER_Basics.rst
…
CHAPTER_CellLib.rst
write_verilog: emit
initial $display
correctly.
2024-01-11 13:13:04 +01:00
CHAPTER_Eval.rst
…
CHAPTER_Intro.rst
…
CHAPTER_Memorymap.rst
docs: reflow memory map
2023-06-19 12:05:51 +12:00
CHAPTER_Optimize.rst
…
CHAPTER_Overview.rst
…
CHAPTER_Prog.rst
Remove docs dependency on yosys repo (
#3558
)
2022-11-24 15:56:44 +01:00
CHAPTER_Techmap.rst
…
CHAPTER_Verilog.rst
…
cmd_ref.rst
…
conf.py
…
index.rst
Initial version of memory mapping doc
2023-05-26 09:36:01 +12:00
literature.bib
…
requirements.txt
…
