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YosysHQ.yosys/techlibs/xilinx
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Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
..
tests
Add pattern detection support for DSP48E1 model, check against vendor
2019-09-18 10:45:04 -07:00
.gitignore
…
abc9_map.v
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
abc9_model.v
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
abc9_unmap.v
Fix merge issues
2019-10-04 17:21:14 -07:00
abc9_xc7_nowide.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_xc7.box
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
abc9_xc7.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
…
brams_init.py
…
cells_map.v
Use abc_{map,unmap,model}.v
2019-08-20 12:39:11 -07:00
cells_sim.v
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
cells_xtra.py
Remove DSP48E1 from *_cells_xtra.v
2019-10-04 17:26:42 -07:00
dsp_map.v
D is 25 bits not 24 bits wide
2019-09-19 15:55:49 -07:00
lut_map.v
…
lutrams_map.v
…
lutrams.txt
…
Makefile.inc
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
mux_map.v
…
synth_xilinx.cc
abc -> abc9
2019-10-04 17:56:38 -07:00
xc6s_brams_bb.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
xc6s_brams_map.v
…
xc6s_brams.txt
…
xc6s_cells_xtra.v
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00
xc6s_ff_map.v
synth_xilinx: Support latches, remove used-up FF init values.
2019-09-30 12:52:43 +02:00
xc6v_cells_xtra.v
Remove DSP48E1 from *_cells_xtra.v
2019-10-04 17:26:42 -07:00
xc7_brams_bb.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
xc7_brams_map.v
…
xc7_brams.txt
…
xc7_cells_xtra.v
Remove DSP48E1 from *_cells_xtra.v
2019-10-04 17:26:42 -07:00
xc7_ff_map.v
synth_xilinx: Support latches, remove used-up FF init values.
2019-09-30 12:52:43 +02:00
xcu_cells_xtra.v
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
2019-09-30 12:52:43 +02:00