github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-24 19:42:18 +00:00
Code Issues Releases Wiki Activity
YosysHQ.yosys/techlibs/ice40
History
David Shah a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning 
ice40: Demote conflicting FF init values to a warning
2020-01-18 09:47:17 +00:00
..
tests
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
2019-08-12 12:06:45 -07:00
.gitignore
Initialization support for all iCE40 bram modes
2015-04-26 08:39:31 +02:00
abc9_hx.box
Cleanup ice40 boxes
2019-12-31 18:29:37 -08:00
abc9_hx.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_lp.box
Cleanup ice40 boxes
2019-12-31 18:29:37 -08:00
abc9_lp.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_model.v
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
abc9_u.box
Cleanup ice40 boxes
2019-12-31 18:29:37 -08:00
abc9_u.lut
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
arith_map.v
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
2019-12-09 12:45:22 -08:00
brams_init.py
Switched to Python 3
2015-08-22 09:59:33 +02:00
brams_map.v
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
2019-02-28 16:23:40 -08:00
brams.txt
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
cells_map.v
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
cells_sim.v
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
2019-10-23 18:44:34 +01:00
dsp_map.v
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
2019-08-08 12:56:05 -07:00
ice40_braminit.cc
substr() -> compare()
2019-08-07 12:20:08 -07:00
ice40_ffinit.cc
ice40: Demote conflicting FF init values to a warning
2019-12-31 02:38:10 +01:00
ice40_ffssr.cc
ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-08 22:46:28 +01:00
ice40_opt.cc
Valid to have attribute starting with SB_CARRY.
2020-01-04 19:00:44 +01:00
latches_map.v
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Makefile.inc
Makefile: don't assume python is called python3
2019-10-19 14:04:52 +08:00
synth_ice40.cc
synth_ice40: call wreduce before mul2dsp
2020-01-17 15:41:55 -08:00