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15902d495f8767fe86bbac1826cbedd1202264ef
YosysHQ.yosys
/
techlibs
/
common
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Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
...
Signed-off-by: Clifford Wolf <
clifford@clifford.at
>
2018-02-23 13:14:47 +01:00
..
.gitignore
…
adff2dff.v
…
cellhelp.py
Progress on cell help messages
2015-10-17 02:35:19 +02:00
cells.lib
…
dff2ff.v
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
Makefile.inc
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
pmux2mux.v
…
prep.cc
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
simcells.v
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
simlib.v
Add $allconst and $allseq cell types
2018-02-23 13:14:47 +01:00
synth.cc
Added "prep -auto-top" and "synth -auto-top"
2016-07-11 11:40:55 +02:00
techmap.v
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00