github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-04 07:10:19 +00:00
Code Issues Releases Wiki Activity
Files
159701962a3136697bafcf9d313c02ca0737fb52
YosysHQ.yosys/backends/verilog
History
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00