Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. ...

Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)

2019-02-25 16:18:13 -08:00

..

aiger

Add "write_aiger -I -O -B"

2018-11-12 09:27:33 +01:00

blif

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

btor

Minor style fixes

2018-12-18 20:02:39 +01:00

edif

Add "write_edif -gndvccy"

2019-01-17 13:33:11 +01:00

firrtl

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

ilang

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

intersynth

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

json

Merge pull request #591 from hzeller/virtual-override

2018-08-15 14:05:38 +02:00

protobuf

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

simplec

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

smt2

Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::get_id() behavior)

2019-02-06 16:35:59 +01:00

smv

Minor update

2018-10-15 13:54:12 -04:00

spice

Consistent use of 'override' for virtual methods in derived classes.

2018-07-20 23:51:06 -07:00

table

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

verilog

Instead of INIT param on cells, use initial statement with hier ref as

2019-02-17 12:18:12 -08:00