Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling ...

- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements

2021-05-25 16:16:46 -04:00

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.gitignore

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aes_kexp128.v

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always01.v

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always02.v

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always03.v

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arraycells.v

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arrays01.v

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arrays02.sv

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asgn_binop.sv

sv: support remaining assignment operators

2021-05-25 16:15:57 -04:00

attrib01_module.v

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attrib02_port_decl.v

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attrib03_parameter.v

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attrib04_net_var.v

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attrib05_port_conn.v.DISABLED

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attrib06_operator_suffix.v

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attrib07_func_call.v.DISABLED

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attrib08_mod_inst.v

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attrib09_case.v

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carryadd.v

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case_expr_const.v

verilog: fix case expression sign and width handling

2021-05-25 16:16:46 -04:00

case_expr_non_const.v

verilog: fix case expression sign and width handling

2021-05-25 16:16:46 -04:00

const_branch_finish.v

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const_fold_func.v

verilog: refactored constant function evaluation

2021-02-04 10:18:27 -05:00

const_func_shadow.v

verilog: refactored constant function evaluation

2021-02-04 10:18:27 -05:00

constmuldivmod.v

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constpower.v

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defvalue.sv

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dff_different_styles.v

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dff_init.v

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dynslice.v

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fiedler-cooley.v

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forgen01.v

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forgen02.v

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forloops.v

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fsm.v

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func_block.v

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func_recurse.v

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func_width_scope.v

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genblk_collide.v

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genblk_dive.v

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genblk_order.v

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genblk_port_shadow.v

verlog: allow shadowing module ports within generate blocks

2021-02-07 11:48:39 -05:00

generate.v

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graphtest.v

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hierarchy.v

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hierdefparam.v

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i2c_master_tests.v

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ifdef_1.v

verilog: fix handling of nested ifdef directives

2021-03-01 12:28:33 -05:00

ifdef_2.v

verilog: fix handling of nested ifdef directives

2021-03-01 12:28:33 -05:00

implicit_ports.v

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local_loop_var.sv

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localparam_attr.v

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loop_var_shadow.v

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loops.v

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macro_arg_spaces.sv

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macro_arg_surrounding_spaces.v

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macros.v

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mem2reg.v

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mem_arst.v

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memory.v

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module_scope.v

verilog: support module scope identifiers in parametric modules

2021-03-16 11:01:30 -04:00

multiplier.v

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muxtree.v

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named_genblk.v

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nested_genblk_resolve.v

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omsp_dbg_uart.v

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operators.v

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param_attr.v

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paramods.v

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partsel.v

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process.v

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realexpr.v

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repwhile.v

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retime.v

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rotate.v

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run-test.sh

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scopes.v

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signedexpr.v

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sincos.v

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specify.v

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string_format.v

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subbytes.v

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task_func.v

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undef_eqx_nex.v

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unnamed_block_decl.sv

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usb_phy_tests.v

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values.v

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verilog_primitives.v

verilog: fix buf/not primitives with multiple outputs

2021-03-17 11:44:03 -04:00

vloghammer.v

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wandwor.v

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wreduce.v

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xfirrtl

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