Jannis Harder 1251e92e3a Add $input_port and $connect cell types

2025-09-17 13:56:46 +02:00

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choices

Merge pull request #4789 from YosysHQ/emil/sklansky-adder

2024-12-03 11:33:13 +01:00

.gitignore

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abc9_map.v

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abc9_model.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

abc9_unmap.v

abc9: fix SCC issues (#2694)

2021-03-29 22:01:57 -07:00

adff2dff.v

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cellhelp.py

cellhelp.py: Cells can have tags

2024-10-15 07:35:41 +13:00

cells.lib

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cmp2lcu.v

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cmp2lut.v

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cmp2softlogic.v

techlibs: Add cmp2softlogic.v to common

2023-11-13 10:42:12 +01:00

dff2ff.v

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gate2lut.v

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gen_fine_ffs.py

simcells: Apply group tags

2024-10-15 07:35:40 +13:00

Makefile.inc

techmap: add a Sklansky option for $lcu mapping

2024-12-02 11:34:58 +01:00

mul2dsp.v

Fix files with CRLF line endings

2021-06-09 12:16:33 +02:00

pmux2mux.v

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prep.cc

Remove .c_str() from stringf parameters

2025-09-01 23:34:42 +00:00

simcells.v

Docs: Assert cell has group

2024-10-15 07:35:40 +13:00

simlib.v

Add $input_port and $connect cell types

2025-09-17 13:56:46 +02:00

smtmap.v

Add smtmap.v describing the smt2 backend's behavior for undef bits

2022-10-20 15:48:18 +02:00

synth.cc

Remove .c_str() from stringf parameters

2025-09-01 23:34:42 +00:00

techmap.v

Add $input_port and $connect cell types

2025-09-17 13:56:46 +02:00