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YosysHQ.yosys/techlibs/intel_alm
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Dan Ravensloft 1a07b330f8 intel_alm: Add multiply signedness to cells 
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
2020-08-26 22:50:16 +02:00
..
common
intel_alm: Add multiply signedness to cells
2020-08-26 22:50:16 +02:00
cyclonev
intel: move Cyclone V support to intel_alm
2020-08-20 18:25:05 +02:00
Makefile.inc
intel: move Cyclone V support to intel_alm
2020-08-20 18:25:05 +02:00
synth_intel_alm.cc
intel_alm: Add multiply signedness to cells
2020-08-26 22:50:16 +02:00