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1af1cebb64b5d8d3f0a66d01d05762a15b3bc0db
YosysHQ.yosys
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techlibs
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Clifford Wolf
a860efa8ac
Implemented same div-by-zero behavior as found in other synthesis tools
2013-08-15 21:00:06 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
blackbox.sed
initial import
2013-01-05 11:13:26 +01:00
Makefile.inc
Added EXTRA_TARGETS Makefile variable
2013-03-28 16:53:40 +01:00
simlib.v
Added $lut cells and abc lut mapping support
2013-07-23 16:19:34 +02:00
stdcells_sim.v
initial import
2013-01-05 11:13:26 +01:00
stdcells.v
Implemented same div-by-zero behavior as found in other synthesis tools
2013-08-15 21:00:06 +02:00