Claire Xen 0146d83ed8 Merge pull request #3014 from YosysHQ/claire/fix-vgtest ...

Fix "make vgtest"

2021-09-24 17:50:34 +02:00

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aiger

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arch

abc9: replace cell type/parameters if derived type already processed (#2991)

2021-09-09 10:05:55 -07:00

asicworld

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bind

Add support for parsing the SystemVerilog 'bind' construct

2021-07-16 09:31:39 -04:00

blif

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bram

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errors

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fsm

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hana

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liberty

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lut

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memfile

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memories

Add opt_mem_widen pass.

2021-08-14 01:06:23 +02:00

opt

memory_share: Add -nosat and -nowiden options.

2021-08-14 00:09:04 +02:00

opt_share

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proc

proc_prune: Make assign removal and promotion per-bit, remember promoted bits.

2021-08-14 15:26:11 +02:00

realmath

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rpc

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sat

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select

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share

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simple

Fix "make vgtest" so it runs to the end (but now it fails ;)

2021-09-23 14:54:28 +02:00

simple_abc9

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smv

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sva

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svinterfaces

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svtypes

sv: improve support for wire and var with user-defined types

2021-08-12 22:41:41 -06:00

techmap

abc9: make re-entrant (#2993)

2021-09-09 10:06:31 -07:00

tools

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unit

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various

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verilog

sv: support wand and wor of data types

2021-09-21 14:52:28 -04:00

vloghtb

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gen-tests-makefile.sh

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