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YosysHQ.yosys/tests
Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks
This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
2021-02-07 11:48:39 -05:00
..
2019-07-16 12:44:26 -07:00
2020-09-21 15:07:02 +02:00
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2021-01-18 17:31:22 +01:00
2020-08-07 13:21:03 +02:00
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