Clifford Wolf 1dcb683fcb Write yosys version to output files

2013-11-03 21:41:39 +01:00

..

bitpattern.h

initial import

2013-01-05 11:13:26 +01:00

calc.cc

Fixed signed div/mod in const eval (rounding and stuff)

2013-08-15 18:23:42 +02:00

celltypes.h

Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_

2013-10-18 12:13:34 +02:00

consteval.h

initial import

2013-01-05 11:13:26 +01:00

driver.cc

Write yosys version to output files

2013-11-03 21:41:39 +01:00

log.cc

initial import

2013-01-05 11:13:26 +01:00

log.h

Added log_assert() api

2013-05-24 14:38:36 +02:00

register.cc

Added "clean -purge" and ";;;" support

2013-08-11 13:59:14 +02:00

register.h

Write yosys version to output files

2013-11-03 21:41:39 +01:00

rtlil.cc

Changed NEW_WIRE API to return the wire, not the signal

2013-10-18 14:19:45 +02:00

rtlil.h

Added design->full_selection() helper method

2013-10-27 09:30:58 +01:00

satgen.h

Implemented same div-by-zero behavior as found in other synthesis tools

2013-08-15 21:00:06 +02:00

sigtools.h

Some fixes to improve determinism

2013-08-09 12:42:32 +02:00