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YosysHQ.yosys/techlibs/nexus
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Pepijn de Vos c2d358484f
Gowin: deal with active-low tristate (#2971) 
* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
2021-08-20 21:21:06 +02:00
..
arith_map.v
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
brams_init.vh
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
brams_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
brams.txt
nexus: Add make_transp to BRAMs
2020-10-22 15:11:59 +01:00
cells_map.v
Gowin: deal with active-low tristate (#2971)
2021-08-20 21:21:06 +02:00
cells_sim.v
nexus: Add MULTADDSUB9X9WIDE sim model
2020-12-08 15:49:20 +00:00
cells_xtra.py
nexus: Add DSP simulation model
2020-11-18 10:21:17 +00:00
cells_xtra.v
nexus: Add DSP simulation model
2020-11-18 10:21:17 +00:00
dsp_map.v
nexus: DSP inference support
2020-11-20 08:45:55 +00:00
latches_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
lrams_init.vh
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
lrams_map.v
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
lrams.txt
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
lutrams_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
lutrams.txt
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
Makefile.inc
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
parse_init.vh
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
synth_nexus.cc
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00