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YosysHQ.yosys/frontends/ast
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Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling 
- The case expression and case item expressions are extended to the
  maximum width among them, and are only interpreted as signed if all of
  them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
2021-05-25 16:16:46 -04:00
..
ast.cc
Change the type of current_module to Module
2021-05-13 23:44:48 -04:00
ast.h
verilog: fix case expression sign and width handling
2021-05-25 16:16:46 -04:00
dpicall.cc
dpi: Support for chandle type
2021-01-23 22:24:31 +00:00
genrtlil.cc
verilog: fix case expression sign and width handling
2021-05-25 16:16:46 -04:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
verilog: fix case expression sign and width handling
2021-05-25 16:16:46 -04:00