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YosysHQ.yosys/techlibs/ecp5
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Adam Greig 9e02786d39 Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.
2021-05-12 10:04:34 +01:00
..
tests
ecp5: Add simulation equivalence check for Diamond FF implementations
2019-08-30 13:27:36 +01:00
.gitignore
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
arith_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
brams_connect.py
ecp5: Add support for mapping 36-bit wide PDP BRAMs
2019-10-01 13:46:36 +01:00
brams_init.py
…
brams_map.v
remove unused parameters
2020-03-06 16:45:36 +01:00
brams.txt
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
2020-02-06 16:52:51 +00:00
cells_bb.v
Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.
2021-05-12 10:04:34 +01:00
cells_ff.vh
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
cells_io.vh
ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
2019-08-30 10:05:09 +00:00
cells_map.v
ecp5: Use dfflegalize.
2020-07-05 18:49:41 +02:00
cells_sim.v
ecp5: TRELLIS_FF bypass path only in async mode
2020-05-14 10:33:56 -07:00
dsp_map.v
ecp5: Force SIGNED ports to be 1 bit
2020-04-16 16:38:19 +01:00
ecp5_gsr.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
latches_map.v
ecp5: Add latch inference
2018-10-19 15:16:40 +01:00
lutrams_map.v
synth_ecp5: rename dram to lutram everywhere.
2019-07-16 20:45:12 +00:00
lutrams.txt
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
2020-02-06 16:52:51 +00:00
Makefile.inc
ecp5: Use dfflegalize.
2020-07-05 18:49:41 +02:00
synth_ecp5.cc
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00