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YosysHQ.yosys/techlibs/nexus
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gatecat cae905f551 Blackbox all whiteboxes after synthesis 
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
..
arith_map.v
nexus: More efficient CO mapping
2020-12-02 17:08:39 +00:00
brams_init.vh
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
brams_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
brams.txt
nexus: Add make_transp to BRAMs
2020-10-22 15:11:59 +01:00
cells_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
cells_sim.v
nexus: Add MULTADDSUB9X9WIDE sim model
2020-12-08 15:49:20 +00:00
cells_xtra.py
nexus: Add DSP simulation model
2020-11-18 10:21:17 +00:00
cells_xtra.v
nexus: Add DSP simulation model
2020-11-18 10:21:17 +00:00
dsp_map.v
nexus: DSP inference support
2020-11-20 08:45:55 +00:00
latches_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
lrams_init.vh
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
lrams_map.v
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
lrams.txt
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
lutrams_map.v
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
lutrams.txt
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
Makefile.inc
nexus: Add LRAM inference
2020-12-07 13:27:17 +00:00
parse_init.vh
synth_nexus: Initial implementation
2020-10-15 08:52:15 +01:00
synth_nexus.cc
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00