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YosysHQ.yosys/frontends/verilog
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Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
..
.gitignore
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-08-11 13:34:10 +02:00
const2ast.cc
Remove .c_str() calls from parameters to log_file_warning()
2025-09-16 23:03:45 +00:00
Makefile.inc
verilog: fix build dependency graph
2025-08-11 13:34:10 +02:00
preproc.cc
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
preproc.h
preproc: formatting
2025-08-11 13:34:10 +02:00
verilog_error.cc
Use C++ stringf machinery in verilog_error
2025-09-12 06:21:56 +00:00
verilog_error.h
Use C++ stringf machinery in verilog_error
2025-09-12 06:21:56 +00:00
verilog_frontend.cc
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
verilog_frontend.h
const2ast: fix for consistency with previous diagnostics behavior
2025-08-11 13:34:10 +02:00
verilog_lexer.h
verilog_lexer: refactor
2025-08-11 13:34:10 +02:00
verilog_lexer.l
verilog: Bufnorm cell backend and frontend support
2025-09-17 14:01:09 +02:00
verilog_location.h
verilog: Fix missing sstream include
2025-08-21 08:26:20 +01:00
verilog_parser.y
verilog_parser: replace manual AST node allocation with typed midrule actions
2025-09-13 11:23:42 +08:00