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Krystine Sherwin
b3024289c6
Docs: Force read_verilog to avoid verific header
2024-04-13 11:33:04 +12:00
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axis
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extensions
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fifo
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intro
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macc
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macro_commands
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opt
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scrambler
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selections
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show
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stubnets
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synth_flow
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techmap
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.gitignore
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primetest.v
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