Clifford Wolf adcda6817e Added smtc "final" statement

2016-08-27 14:30:36 +02:00

..

blif

Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior

2016-07-08 11:51:04 +02:00

btor

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

edif

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

ilang

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

intersynth

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

json

write_json: also write module attributes.

2016-07-12 06:32:04 +00:00

smt2

Added smtc "final" statement

2016-08-27 14:30:36 +02:00

smv

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

spice

Also escape "=" in spice output

2016-05-20 16:43:13 +02:00

verilog

Bugfix in partial mem write handling in verilog back-end

2016-08-20 13:06:06 +02:00