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YosysHQ.yosys/tests/various
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Tobias Wölfel 8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
2019-06-19 12:47:48 +02:00
..
.gitignore
Added tests/various/.gitignore
2014-07-26 17:43:41 +02:00
attrib05_port_conn.v
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
2019-06-04 10:42:42 +02:00
attrib05_port_conn.ys
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
2019-06-04 10:42:42 +02:00
attrib07_func_call.v
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
2019-06-04 10:42:42 +02:00
attrib07_func_call.ys
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
2019-06-04 10:42:42 +02:00
chparam.sh
Add tests/various/chparam.sh
2019-05-06 16:03:15 +02:00
constmsk_test.v
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
constmsk_test.ys
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
constmsk_testmap.v
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
elab_sys_tasks.sv
Initial implementation of elaboration system tasks
2019-05-03 03:10:43 +03:00
elab_sys_tasks.ys
Initial implementation of elaboration system tasks
2019-05-03 03:10:43 +03:00
hierarchy.sh
Fix tests
2019-04-21 11:40:20 +02:00
muxcover.ys
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
2019-04-15 17:52:45 -07:00
opt_rmdff.v
Fix init
2019-05-24 18:43:26 -07:00
opt_rmdff.ys
Add more tests
2019-05-24 18:33:18 -07:00
pmux2shiftx.v
Improvements in pmux2shiftx
2019-04-20 00:38:25 +02:00
pmux2shiftx.ys
Updaye pmux2shiftx test
2019-04-22 16:17:43 +02:00
reg_wire_error.sv
Modified errors into warnings
2018-06-05 18:03:22 +03:00
reg_wire_error.ys
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00
run-test.sh
Address requested changes - don't require non-$ name.
2019-02-22 16:06:10 -08:00
specify.v
More testing
2019-05-03 15:54:25 -07:00
specify.ys
Improve tests/various/specify.ys
2019-05-06 12:26:15 +02:00
submod_extract.ys
Added tests/various/submod_extract.ys
2014-07-26 17:22:18 +02:00
unpacked_arrays.sv
Unpacked array declaration using size
2019-06-19 12:47:48 +02:00
unpacked_arrays.ys
Unpacked array declaration using size
2019-06-19 12:47:48 +02:00