Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3

2014-07-23 09:34:47 +02:00

..

abc

Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3

2014-07-23 09:34:47 +02:00

cmds

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2014-07-22 20:58:44 +02:00

fsm

SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands

2014-07-22 23:11:36 +02:00

hierarchy

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2014-07-22 20:58:44 +02:00

memory

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2014-07-22 20:58:44 +02:00

opt

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2014-07-22 20:58:44 +02:00

proc

Fixed memory corruption with new SigSpec API in proc_mux

2014-07-22 22:54:39 +02:00

sat

Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3

2014-07-23 09:34:47 +02:00

techmap

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2014-07-22 20:58:44 +02:00