Miodrag Milanovic 714603bf69 synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

..

tests

Update filenames and location for test script

2025-09-25 15:44:05 +01:00

arith_map_ccu2c.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

arith_map_ccu2d.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

arith_map_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

brams_8kc.txt

lattice: Disable broken port configuration in bram inference

2023-12-21 10:47:40 +01:00

brams_16kd.txt

Create synth_lattice

2023-08-23 10:53:21 +02:00

brams_map_8kc.v

lattice: Fix mapping onto DP8KC for data width 1 or 2

2023-12-20 23:42:12 +01:00

brams_map_16kd.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

brams_map_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

brams_nexus.txt

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

ccu2c_sim.vh

Create synth_lattice

2023-08-23 10:53:21 +02:00

ccu2d_sim.vh

Create synth_lattice

2023-08-23 10:53:21 +02:00

cells_bb_ecp5.v

Special DP16KD model is required

2025-09-25 15:38:55 +01:00

cells_bb_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

cells_bb_xo2.v

enable more primitives supported with nextpnr

2023-08-25 11:45:25 +02:00

cells_bb_xo3.v

enable more primitives supported with nextpnr

2023-08-25 11:45:25 +02:00

cells_bb_xo3d.v

enable more primitives supported with nextpnr

2023-08-25 11:45:25 +02:00

cells_ff.vh

Create synth_lattice

2023-08-23 10:53:21 +02:00

cells_io.vh

Create synth_lattice

2023-08-23 10:53:21 +02:00

cells_map_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

cells_map_trellis.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

cells_sim_ecp5.v

Special DP16KD model is required

2025-09-25 15:38:55 +01:00

cells_sim_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

cells_sim_xo2.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

cells_sim_xo3.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

cells_sim_xo3d.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

cells_xtra_nexus.py

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

cells_xtra.py

Special DP16KD model is required

2025-09-25 15:38:55 +01:00

common_sim.vh

Delete synth_ecp5

2025-09-25 15:44:03 +01:00

dsp_map_18x18.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

dsp_map_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

latches_map.v

Create synth_lattice

2023-08-23 10:53:21 +02:00

lattice_gsr.cc

ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech

2023-08-22 10:50:11 +02:00

lrams_map_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

lrams_nexus.txt

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

lutrams_map_nexus.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

lutrams_map_trellis.v

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

lutrams_nexus.txt

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

lutrams_trellis.txt

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

Makefile.inc

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

parse_init.vh

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00

synth_lattice.cc

synth_nexus to synth_lattice

2025-09-26 19:45:03 +01:00