Clifford Wolf a330c68363 Fix handling of task output ports in clocked always blocks, fixes #857 ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2019-03-07 22:44:37 -08:00

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asicworld

Fix FIRRTL to Verilog process instance subfield assignment.

2019-02-25 16:18:13 -08:00

bram

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errors

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

2018-10-25 02:37:56 +03:00

fsm

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hana

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lut

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

memories

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opt

Fix WREDUCE on FF not fixing ARST_VALUE parameter.

2019-02-22 10:30:42 -08:00

realmath

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sat

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share

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simple

Fix handling of task output ports in clocked always blocks, fixes #857

2019-03-07 22:44:37 -08:00

smv

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sva

Squelch a little more trailing whitespace

2018-12-29 12:46:54 +01:00

svinterfaces

Add missing .gitignore

2018-12-06 07:29:37 +01:00

techmap

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tools

Hotfix for "make test"

2019-02-28 20:26:54 -08:00

unit

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various

Address requested changes - don't require non-$ name.

2019-02-22 16:06:10 -08:00

vloghtb

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