github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-26 20:23:59 +00:00
Code Issues Releases Wiki Activity
Files
2cef48bf2cb78aaa4b4dd1ea0bc064c8d12e7147
YosysHQ.yosys/passes/hierarchy
History
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
2021-10-25 18:25:50 -07:00
..
hierarchy.cc
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
Makefile.inc
Rename "singleton" pass to "uniquify"
2017-08-20 12:31:50 +02:00
submod.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
uniquify.cc
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00