Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping ...

Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being
true dual port (or 18bit*512 when simple dual port), the other is
16bit*2K.

Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and
32Kbit BRAM with 8bit width are not support yet.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

2021-12-17 20:28:22 +08:00

..

.gitignore

Moved all tests in arch sub directory

2019-10-18 11:06:12 +02:00

add_sub.ys

Share common tests

2019-10-18 12:19:59 +02:00

blockram.ys

anlogic: support BRAM mapping

2021-12-17 20:28:22 +08:00

counter.ys

Call equiv_opt with -multiclock and -assert

2019-12-31 18:39:32 -08:00

dffs.ys

Replace opt_rmdff with opt_dff.

2020-08-07 13:21:03 +02:00

fsm.ys

Simplify breaking tests/arch/*/fsm.ys tests

2020-03-20 11:25:17 -07:00

latches.ys

anlogic: Use dfflegalize.

2020-07-14 05:02:50 +02:00

logic.ys

Share common tests

2019-10-18 12:19:59 +02:00

lutram.ys

anlogic: support BRAM mapping

2021-12-17 20:28:22 +08:00

mux.ys

Share common tests

2019-10-18 12:19:59 +02:00

run-test.sh

tests: Centralize test collection and Makefile generation

2020-09-21 15:07:02 +02:00

shifter.ys

Share common tests

2019-10-18 12:19:59 +02:00

tribuf.ys

Share common tests

2019-10-18 12:19:59 +02:00