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YosysHQ.yosys/techlibs/xilinx
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Eddie Hung c7f5091c2f Reduce diff with master
2019-06-12 09:34:41 -07:00
..
tests
Improved xilinx "bram1" test
2015-04-09 17:12:12 +02:00
.gitignore
Added support for initialized xilinx brams
2015-04-06 17:07:10 +02:00
abc.box
Add flops as blackboxes
2019-05-31 18:11:46 -07:00
abc.lut
Some more realistic delays...
2019-05-29 22:55:34 -07:00
arith_map.v
Instead of MUXCY/XORCY use CARRY4 (with timing)
2019-05-21 16:19:45 -07:00
brams_bb.v
Add (* abc_flop_q *) to brams_bb.v
2019-06-04 11:53:51 -07:00
brams_init.py
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
brams_map.v
Revert BRAM WRITE_MODE changes.
2019-03-04 09:22:22 -08:00
brams.txt
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
cells_map.v
Remove wide mux inference
2019-06-12 09:20:46 -07:00
cells_sim.v
Disable dist RAM boxes due to comb loop
2019-06-11 12:02:51 -07:00
cells_xtra.sh
Typo
2019-05-28 09:36:01 -07:00
cells_xtra.v
Add whitebox support to DRAM
2019-05-23 08:58:57 -07:00
drams_map.v
Xilinx DRAMS: RAM64X1D, RAM128X1D
2015-04-09 13:37:07 +02:00
drams.txt
Add "min bits" and "min wports" to xilinx dram rules
2019-05-23 11:32:28 -07:00
ff_map.v
Cleanup
2019-06-05 12:28:46 -07:00
lut_map.v
Changes required for VPR place and route synth_xilinx.
2019-03-01 12:02:27 -08:00
Makefile.inc
Remove wide mux inference
2019-06-12 09:20:46 -07:00
synth_xilinx.cc
Reduce diff with master
2019-06-12 09:34:41 -07:00