1
0
mirror of synced 2026-02-23 07:51:45 +00:00
Files
YosysHQ.yosys/backends/verilog
whitequark e95a8ba763 write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
2020-02-06 16:22:42 +00:00
..
2013-01-05 11:13:26 +01:00