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Udi Finkelstein
536ae16c3a
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
...
meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
..
syntax_err01.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err02.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err03.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err04.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err05.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err06.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err07.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err08.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err09.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err10.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err11.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err12.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
syntax_err13.v
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00