Eddie Hung 35fd9b0473 Merge remote-tracking branch 'origin/master' into xaig_dff

2019-07-02 12:35:45 -07:00

..

aiger

Refactor and cope with new abc_flop format

2019-07-01 11:50:34 -07:00

ast

Add "read_verilog -pwires" feature, closes #1106

2019-06-19 14:38:50 +02:00

blif

Add missing "[options]" to read_blif help

2019-02-08 12:41:39 -08:00

ilang

Make the generated *.tab.hh include all the headers needed to define the union.

2019-05-14 21:07:26 -07:00

json

Add upto and offset to JSON ports

2019-06-21 19:47:25 +02:00

liberty

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

verific

Only support Symbiotic EDA flavored Verific

2019-06-02 10:14:50 +02:00

verilog

Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53

2019-07-02 11:36:26 +02:00