Zachary Snow 10a6bc9b81 verilog: fix sizing of ports with int types in module headers ...

Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.

2021-03-01 13:39:05 -05:00

..

aiger

Provide an integer implementation of decimal_digits().

2021-02-01 11:23:44 -08:00

ast

Merge pull request #2615 from zachjs/genrtlil-conflict

2021-03-01 08:10:19 -08:00

blif

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

json

frontend: json: parse negative values

2021-02-23 00:26:11 +01:00

liberty

Use C++11 final/override keywords.

2020-06-18 23:34:52 +00:00

rpc

Fix argument handling in connect_rpc

2020-10-19 13:40:57 +02:00

rtlil

rtlil: remove dotted identifiers.

2020-11-25 16:47:20 +00:00

verific

Merge pull request #2574 from dh73/master

2021-02-15 17:49:11 +01:00

verilog

verilog: fix sizing of ports with int types in module headers

2021-03-01 13:39:05 -05:00